1. Field of the Invention
The present invention relates to a phase swallow device and a signal generator, and more particularly to a phase swallow device for outputting a clock with lower jitter and a signal generator using the same.
2. Description of the Related Art
FIG. 1 illustrates the architecture of a conventional signal generator. The signal generator 10 is used to generate a frequency synthesis clock. The frequency of the synthesis clock is adjusted according to user's requirements. The signal generator 10 includes a multi-phase clock generator 11, a multiplexer (MUX) 12, a phase-swallow control unit 14, and a clock selector 15. The multi-phase clock generator 11 generates a plurality of multi-phase reference clocks CK0, CK1 . . . CKn-1 with same frequency according to a reference clock. FIG. 2 shows waveforms of eight multi-phase reference clocks CK0, CK1 . . . CK7. The multiplexer 12 receives the plurality of multi-phase reference clocks CK0, CK1 . . . CKn-1, and selects one of the multi-phase reference clocks as an output clock according to a phase selecting signal. The phase-swallow control unit 14 generates a swallow control signal (SCS) according to a swallow value. The clock selector 15 outputs the phase selecting signal according to the swallow control signal SCS. The clock selector 15 may be a counter triggered by the swallow control signal SCS, and the counter is used for counting the swallow control signal SCS and outputs the counting value as the phase selecting signal. When the swallow control signal SCS is enabled, for example from 0 to 1, the value of the counter is increased. Thus, the multiplexer 12 selects the clock with next phase as the output clock. Consequently, the frequency of the output clock of the signal generator 10 is finely adjusted according to the number of enabling the swallow control signal SCS.
In general, the conventional phase-swallow control unit utilizes a sigma-delta modulator to achieve the requirements of precisely controlling the output frequency and making the cycle jitter small. Taking the one-order sigma-delta modulator as an example, the embodiment thereof may be an accumulator having a circuit area larger than that of the typical logic device (e.g., AND gate, OR gate, or flip-flop).
To meet the circuit design requirement of small circuit area and dimension, the conventional phase-swallow control unit utilizes a counter, which may be regarded as being composed of a plurality of flip-flops, to achieve this requirement, as shown in FIG. 3. FIG. 3 illustrates a block diagram showing a conventional phase-swallow control unit. Referring to this drawing, the phase-swallow control unit 14 includes a counter 31, a comparator 32, and a register 33. The counter 31 counts the pulse number of a counting clock, and outputs the counting value to the comparator 32. The register 33 stores the swallow value. The comparator 32 compares the counting value outputted from the counter 31 with the swallow value stored in the register 33. That is, when the counting value is smaller than the swallow value, the swallow control signal SCS is enabled, for example 1; or otherwise the swallow control signal SCS is disabled, for example 0, when the counting value is greater than or equal to the swallow value. Consequently, as shown in FIG. 3, the low bit of the counting value is compared to the low bit of the swallow value, and the high bit of the counting value is compared to the high bit of the swallow value.
In the architecture of FIG. 3, the phase thereof is continuously swallowed. For example, if the phase difference equals three phases, the conventional phase swallow method is performed by swallowing one phase in each clock cycle of the continuous three clock cycles. Consequently, the cycle-cycle jitter of the output clock of the signal generator 10 is large. According to the system requirement, the output clock may be divided by a proper value so as to obtain the required frequency. That is, a frequency divider (not shown) is utilized to receive and then divide the clock outputted from the multiplexer 12. When three phases are to be continuously swallowed in 8 pulse cycles and the frequency divider is divided by 3, the maximum cycle-cycle jitter is 3ΔT, wherein ΔT is the phase difference between two adjacent multi-phase reference clocks. In addition, as the swallowed phases become greater, the maximum cycle-cycle jitter becomes larger.